GNU bug report logs - #66252
[PATCH 0/3] riscv: Introduce Pseudo NMI

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Package: guix-patches;

Reported by: Xu Lu <luxu.kernel <at> bytedance.com>

Date: Thu, 28 Sep 2023 10:17:02 UTC

Severity: normal

Tags: patch

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Report forwarded to guix-patches <at> gnu.org:
bug#66252; Package guix-patches. (Thu, 28 Sep 2023 10:17:02 GMT) Full text and rfc822 format available.

Acknowledgement sent to Xu Lu <luxu.kernel <at> bytedance.com>:
New bug report received and forwarded. Copy sent to guix-patches <at> gnu.org. (Thu, 28 Sep 2023 10:17:02 GMT) Full text and rfc822 format available.

Message #5 received at submit <at> debbugs.gnu.org (full text, mbox):

From: Xu Lu <luxu.kernel <at> bytedance.com>
To: guix-patches <at> gnu.org
Cc: Xu Lu <luxu.kernel <at> bytedance.com>
Subject: [PATCH 0/3] riscv: Introduce Pseudo NMI
Date: Thu, 28 Sep 2023 17:34:13 +0800
The existing riscv kernel still lacks a NMI mechanism. It now
disables interrupts via per cpu control register CSR_STATUS,
the SIE bit of which controls the enablement of all interrupts
of whole cpu.

This patch series introduces a pseudo NMI mechanism in RISC-V
by switching interrupt disable way to another per cpu control
register CSR_IE. This register controls the enablement of each
seperate interrupt. Every bit of CSR_IE corresponds to a single
major interrupt and a clear bit means disablement of corresponding
interrupt. The main procedure of implementing pseudo NMI via
CSR_IE consists of three steps:

Stage1:
Make CSR_IE register part of thread context to avoid irq status
inconsistence after context switch.

Stage2:
Switch to CSR_IE masking when disabling irqs. When interrupts
are disabled, all bits of CSR_IE corresponding to normal
interrupts are cleared while bits corresponding to NMIs are
still kept as ones.

Stage3:
Enable NMIs mannualy during exceptions and normal interrupts as
hardware automatically disables all interrupts when trapped into
supervisor mode.

Xu Lu (3):
  riscv: Enable NMIs during normal interrupt handling
  riscv: Request pmu overflow interrupt as NMI
  riscv: Enable CONFIG_RISCV_PSEUDO_NMI in default

 arch/riscv/Kconfig               |  2 +-
 arch/riscv/kernel/traps.c        | 44 +++++++++++++++++++++++---------
 drivers/irqchip/irq-riscv-intc.c |  2 ++
 drivers/perf/riscv_pmu_sbi.c     | 23 ++++++++++++++---
 4 files changed, 54 insertions(+), 17 deletions(-)


base-commit: 2dde18cd1d8fac735875f2e4987f11817cc0bc2c
prerequisite-patch-id: 0f865f6b1e0e30e051fd516afeb4cbdf687fa2e3
prerequisite-patch-id: 6632047c24a21a9426d54145f499a9ec4f6fb0c6
prerequisite-patch-id: 681d783ad71fe9770787680cb6d4385ae7a1ac05
prerequisite-patch-id: 1aa352fed255df745c4e47b589405bb9fe932efb
prerequisite-patch-id: 579727cfbe5f803335a678b227c31f9ec165df9f
prerequisite-patch-id: 9b616129ab18eb41abcdf007ce7d0d49f9a88d36
prerequisite-patch-id: 6c01bc4284a007d3a8b57b919d41380f2786b156
prerequisite-patch-id: f62067b439c1553c96e3462221a16fc52de2accb
-- 
2.20.1





This bug report was last modified 219 days ago.

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