GNU bug report logs - #46069
[PATCH] gnu: Add SystemC.

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Message #5 received at submit <at> debbugs.gnu.org (full text, mbox):

From: Andrew Miloradovsky <andrew <at> interpretmath.pw>
To: guix-patches <at> gnu.org
Cc: Andrew Miloradovsky <andrew <at> interpretmath.pw>
Subject: [PATCH] gnu: Add SystemC.
Date: Sun, 24 Jan 2021 08:07:40 +0000

* gnu/packages/fpga.scm (systemc): New variable.
---
 gnu/packages/fpga.scm | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 96ba0026f9..ff03b5270d 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -467,3 +467,32 @@ a hardware description and verification language. ")
     (description "This package provides a VHDL compiler and simulator.")
     (home-page "https://github.com/nickg/nvc")
     (license license:gpl3+)))
+
+(define-public systemc
+  (package
+    (name "systemc")
+    (version "2.3.3")
+    (source (origin
+              (method url-fetch)
+              (uri (string-append
+                    "https://accellera.org/images/downloads/standards/"
+                    name "/" name "-" version ".tar.gz"))
+              (sha256
+               (base32
+                "0gvv3xmhiwx1izmzy06yslzqzh6ygrgmw53xqfmyvbz5a6ivk0ap"))))
+    (native-inputs `(("perl" ,perl)))
+    (build-system gnu-build-system)
+    (arguments '(#:configure-flags '("--enable-debug")))
+    (home-page "https://accellera.org/downloads/standards/systemc")
+    (synopsis "Library for event-driven simulation")
+    (description "Reference implementation of IEEE 1666-2011.
+A C++ library for modeling concurrent systems.  It provides a notion of timing
+as well as an event-driven simulations environment.  Due to it’s concurrent
+and sequential nature, SystemC allows the description and integration of
+complex hardware and software components.  To some extent, SystemC can be seen
+as a Hardware Description Language. However, unlike VHDL or Verilog, SystemC
+provides sophisticated mechanisms that offer high abstraction levels on
+components interfaces.  This, in turn, facilitates the integration of systems
+using different abstraction levels.")
+    ;; homepages.cae.wisc.edu/~ece734/SystemC/Esperan_SystemC_tutorial.pdf
+    (license license:asl2.0)))
-- 
2.30.0

Message #8 received at 46069 <at> debbugs.gnu.org (full text, mbox):

From: Andrew Miloradovsky <andrew <at> interpretmath.pw>
To: 46069 <at> debbugs.gnu.org
Cc: Andrew Miloradovsky <andrew <at> interpretmath.pw>
Subject: [PATCH] gnu: Add Verilator.
Date: Sun, 24 Jan 2021 17:45:47 +0000

* gnu/packages/fpga.scm (verilator): New variable.
---
 gnu/packages/fpga.scm | 47 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index ff03b5270d..429e848c31 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -496,3 +496,50 @@ components interfaces.  This, in turn, facilitates the integration of systems
 using different abstraction levels.")
     ;; homepages.cae.wisc.edu/~ece734/SystemC/Esperan_SystemC_tutorial.pdf
     (license license:asl2.0)))
+
+(define-public verilator
+  (package
+    (name "verilator")
+    (version "4.108")
+    (source (origin
+              (method url-fetch)
+              (uri (string-append
+                    "https://github.com/" name "/"
+                    name "/archive/v" version ".tar.gz"))
+              (file-name (string-append name "-" version ".tar.gz"))
+              (sha256
+               (base32
+                "0mbwplrkmp06clm1y3p33n74qrr3rqsc803hzwjs7ralfz2islnf"))))
+    (native-inputs `(("autoconf" ,autoconf)
+                     ("automake" ,automake)
+                     ("gettext" ,gettext-minimal)
+                     ("perl" ,perl)
+                     ("python" ,python)
+                     ("flex" ,flex)
+                     ("bison" ,bison)
+                     ("systemc" ,systemc)))
+    (build-system gnu-build-system)
+    (arguments '(#:configure-flags
+                 (list (string-append "LDFLAGS=-L"
+                                      (assoc-ref %build-inputs "systemc")
+                                      "/lib-linux64"))
+                 #:make-flags
+                 (list (string-append "LDFLAGS=-L"
+                                      (assoc-ref %build-inputs "systemc")
+                                      "/lib-linux64"))
+                 #:phases
+                 (modify-phases %standard-phases
+                   (replace 'bootstrap
+                     (lambda _ (invoke "autoconf"))))
+                 #:test-target "test"))
+    ;; #error "Something failed during ./configure as config_build.h is incomplete.
+    ;; Perhaps you used autoreconf, don't." -- so we won't. ^
+    (home-page "https://www.veripool.org/projects/verilator/")
+    (synopsis "A fast Verilog/SystemVerilog simulator")
+    (description "It compiles SystemVerilog to C++ or SystemC.
+The user writes a little C++/SystemC wrapper file, which instantiates the
+'Verilated' model of the user’s top level module.  These C++/SystemC files are
+then compiled by a C++ compiler (GCC/Clang/etc.).  The resulting executable
+performs the design simulation.  Verilator also supports linking its generated
+libraries, optionally encrypted, into other simulators.")
+    (license license:lgpl3)))
-- 
2.30.0

Message #11 received at 46069 <at> debbugs.gnu.org (full text, mbox):

From: Nicolas Goaziou <mail <at> nicolasgoaziou.fr>
To: Andrew Miloradovsky <andrew <at> interpretmath.pw>
Cc: 46069 <at> debbugs.gnu.org
Subject: Re: [bug#46069] [PATCH] gnu: Add SystemC.
Date: Thu, 28 Jan 2021 14:57:39 +0100

Hello,

Andrew Miloradovsky <andrew <at> interpretmath.pw> writes:

> * gnu/packages/fpga.scm (systemc): New variable.

I applied your patch with the changes detailed below.

> +    (source (origin
> +              (method url-fetch)
> +              (uri (string-append
> +                    "https://accellera.org/images/downloads/standards/"
> +                    name "/" name "-" version ".tar.gz"))

I hard-coded "name" since this is what we usually do in packages.

> +    (home-page "https://accellera.org/downloads/standards/systemc")

I changed home-page so it does not point to the Downloads section
directly.

> +    (synopsis "Library for event-driven simulation")

> +    (description "Reference implementation of IEEE 1666-2011.
> +A C++ library for modeling concurrent systems.  

I reworded a bit the description to it starts with full sentences.

Thank you!

Regards,
-- 
Nicolas Goaziou

Message #16 received at 46069-done <at> debbugs.gnu.org (full text, mbox):

From: Nicolas Goaziou <mail <at> nicolasgoaziou.fr>
To: Andrew Miloradovsky <andrew <at> interpretmath.pw>
Cc: 46069-done <at> debbugs.gnu.org
Subject: Re: [bug#46069] [PATCH] gnu: Add Verilator.
Date: Thu, 28 Jan 2021 15:01:14 +0100

Hello,

Andrew Miloradovsky <andrew <at> interpretmath.pw> writes:

> * gnu/packages/fpga.scm (verilator): New variable.

I added a copyright line for you in "fpga.scm" and applied your patch
with the changes detailed below.

> +    (source (origin
> +              (method url-fetch)
> +              (uri (string-append
> +                    "https://github.com/" name "/"
> +                    name "/archive/v" version ".tar.gz"))

This is an unstable release, so I used git-fetch instead, with the tag
corresponding to the release.

> +    (native-inputs `(("autoconf" ,autoconf)
> +                     ("automake" ,automake)
> +                     ("gettext" ,gettext-minimal)
> +                     ("perl" ,perl)
> +                     ("python" ,python)
> +                     ("flex" ,flex)
> +                     ("bison" ,bison)
> +                     ("systemc" ,systemc)))

I re-ordered native-inputs alphabetically, and moved perl and systemc to
regular inputs instead. I'm not absolutely sure about this change, but
it still compiles. Let me know if this is not appropriate.

> +    (synopsis "A fast Verilog/SystemVerilog simulator")

I tweaked the synopsis so it doesn't start with the "A" article. Running
"guix lint" should warn you about it.

> +    (description "It compiles SystemVerilog to C++ or SystemC.
> +The user writes a little C++/SystemC wrapper file, which instantiates the
> +'Verilated' model of the user’s top level module.  These C++/SystemC files are
> +then compiled by a C++ compiler (GCC/Clang/etc.).  The resulting executable
> +performs the design simulation.  Verilator also supports linking its generated
> +libraries, optionally encrypted, into other simulators.")

I slightly reworded the beginning of the description according to
information from the GitHub repository.

Thank you.

Regards,
-- 
Nicolas Goaziou

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