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From: Simon South <simon@HIDDEN>
To: 60429 <at> debbugs.gnu.org
Subject: [PATCH v2 5/5] gnu: yosys: Update to 0.25.
Date: Sun, 8 Jan 2023 13:31:31 -0500
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* gnu/packages/fpga.scm (yosys): Update to 0.25.
[arguments]: Remove obsolete "fix-iverilog-references" phase.
[inputs]: Add zlib.
[propagated-inputs]: Add gtkwave, python, python-click.
---
gnu/packages/fpga.scm | 35 +++++++++--------------------------
1 file changed, 9 insertions(+), 26 deletions(-)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 785d385621..45cf0e74cf 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -137,16 +137,15 @@ (define-public iverilog
(define-public yosys
(package
(name "yosys")
- (version "0.9")
+ (version "0.25")
(source (origin
(method git-fetch)
(uri (git-reference
(url "https://github.com/YosysHQ/yosys")
- (commit (string-append "yosys-" version))
- (recursive? #t))) ; for the ‘iverilog’ submodule
+ (commit (string-append "yosys-" version))))
(sha256
- (base32
- "0lb9r055h8y1vj2z8gm4ip0v06j5mk7f9zx9gi67kkqb7g4rhjli"))
+ (base32
+ "1j5slm7m02q6n0yv6f3ihv2rgrc4krzcdz6g8v6jmj0gwgh9xi5h"))
(file-name (git-file-name name version))))
(build-system gnu-build-system)
(arguments
@@ -164,26 +163,6 @@ (define-public yosys
(lambda _
(substitute* '("./Makefile")
(("ABCEXTERNAL \\?=") "ABCEXTERNAL = abc"))))
- (add-before 'check 'fix-iverilog-references
- (lambda* (#:key inputs native-inputs #:allow-other-keys)
- (let ((iverilog (search-input-file (or native-inputs inputs)
- "/bin/iverilog")))
- (substitute* '("./manual/CHAPTER_StateOfTheArt/synth.sh"
- "./manual/CHAPTER_StateOfTheArt/validate_tb.sh"
- "./techlibs/ice40/tests/test_bram.sh"
- "./techlibs/ice40/tests/test_ffs.sh"
- "./techlibs/xilinx/tests/bram1.sh"
- "./techlibs/xilinx/tests/bram2.sh"
- "./tests/bram/run-single.sh"
- "./tests/realmath/run-test.sh"
- "./tests/simple/run-test.sh"
- "./tests/techmap/mem_simple_4x1_runtest.sh"
- "./tests/tools/autotest.sh"
- "./tests/vloghtb/common.sh")
- (("if ! which iverilog") "if ! true")
- (("iverilog ") (string-append iverilog " "))
- (("iverilog_bin=\".*\"") (string-append "iverilog_bin=\""
- iverilog "\""))))))
(add-after 'install 'add-symbolic-link
(lambda* (#:key inputs #:allow-other-keys)
;; Previously this package provided a copy of the "abc"
@@ -203,11 +182,15 @@ (define-public yosys
(inputs
(list libffi
readline
- tcl))
+ tcl
+ zlib))
(propagated-inputs
(list abc
graphviz ; for dot
+ gtkwave ; for vcd2fst
psmisc ; for fuser
+ python
+ python-click
xdot
z3)) ; should be in path for yosys-smtbmc
(home-page "https://yosyshq.net/yosys/")
--
2.38.1
guix-patches@HIDDEN:bug#60429; Package guix-patches.
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From: Simon South <simon@HIDDEN>
To: 60429 <at> debbugs.gnu.org
Subject: [PATCH v2 2/5] gnu: yosys: Use new package style.
Date: Sun, 8 Jan 2023 13:31:28 -0500
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* gnu/packages/fpga.scm (yosys)[source]: Use gexp in snippet and don't
explicitly return #t.
[arguments]: Use gexps; use search-input-file to locate executables; simplify
parameters to "configure" phase; don't explicitly return #t from phases.
[native-inputs]: Sort alphabetically.
[inputs]: Sort alphabetically.
---
gnu/packages/fpga.scm | 122 +++++++++++++++++++++---------------------
1 file changed, 60 insertions(+), 62 deletions(-)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 45aadf8ea4..479ca3b061 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -150,77 +150,75 @@ (define-public yosys
(file-name (git-file-name name version))
(modules '((guix build utils)))
(snippet
- '(begin
- (substitute* "Makefile"
- (("ABCREV = .*") "ABCREV = default\n"))
- #t))))
+ #~(begin
+ (substitute* "Makefile"
+ (("ABCREV = .*") "ABCREV = default\n"))))))
(build-system gnu-build-system)
(arguments
- `(#:test-target "test"
- #:make-flags (list "CC=gcc"
- "CXX=g++"
- (string-append "PREFIX=" %output))
- #:phases
- (modify-phases %standard-phases
- (add-before 'configure 'fix-paths
- (lambda _
- (substitute* "./passes/cmds/show.cc"
- (("exec xdot") (string-append "exec " (which "xdot")))
- (("dot -") (string-append (which "dot") " -"))
- (("fuser") (which "fuser")))
- #t))
- (replace 'configure
- (lambda* (#:key inputs (make-flags '()) #:allow-other-keys)
- (apply invoke "make" "config-gcc" make-flags)))
- (add-after 'configure 'prepare-abc
- (lambda* (#:key inputs #:allow-other-keys)
- (let* ((sourceabc (assoc-ref inputs "abc"))
- (sourcebin (string-append sourceabc "/bin"))
- (source (string-append sourcebin "/abc")))
- (mkdir-p "abc")
- (call-with-output-file "abc/Makefile"
- (lambda (port)
- (format port ".PHONY: all\nall:\n\tcp -f abc abc-default\n")))
- (copy-file source "abc/abc")
- (invoke "chmod" "+w" "abc/abc"))))
+ (list
+ #:test-target "test"
+ #:make-flags #~(list "CC=gcc"
+ "CXX=g++"
+ (string-append "PREFIX=" #$output))
+ #:phases
+ #~(modify-phases %standard-phases
+ (add-before 'configure 'fix-paths
+ (lambda* (#:key inputs #:allow-other-keys)
+ (substitute* "./passes/cmds/show.cc"
+ (("exec xdot")
+ (string-append "exec " (search-input-file inputs
+ "/bin/xdot")))
+ (("dot -")
+ (string-append (search-input-file inputs "/bin/dot") " -"))
+ (("fuser")
+ (search-input-file inputs "/bin/fuser")))))
+ (replace 'configure
+ (lambda* (#:key make-flags #:allow-other-keys)
+ (apply invoke "make" "config-gcc" make-flags)))
+ (add-after 'configure 'prepare-abc
+ (lambda* (#:key inputs #:allow-other-keys)
+ (mkdir-p "abc")
+ (call-with-output-file "abc/Makefile"
+ (lambda (port)
+ (format port ".PHONY: all\nall:\n\tcp -f abc abc-default\n")))
+ (copy-file (search-input-file inputs "/bin/abc") "abc/abc")
+ (invoke "chmod" "+w" "abc/abc")))
(add-before 'check 'fix-iverilog-references
- (lambda* (#:key inputs native-inputs #:allow-other-keys)
- (let* ((xinputs (or native-inputs inputs))
- (xdirname (assoc-ref xinputs "iverilog"))
- (iverilog (string-append xdirname "/bin/iverilog")))
- (substitute* '("./manual/CHAPTER_StateOfTheArt/synth.sh"
- "./manual/CHAPTER_StateOfTheArt/validate_tb.sh"
- "./techlibs/ice40/tests/test_bram.sh"
- "./techlibs/ice40/tests/test_ffs.sh"
- "./techlibs/xilinx/tests/bram1.sh"
- "./techlibs/xilinx/tests/bram2.sh"
- "./tests/bram/run-single.sh"
- "./tests/realmath/run-test.sh"
- "./tests/simple/run-test.sh"
- "./tests/techmap/mem_simple_4x1_runtest.sh"
- "./tests/tools/autotest.sh"
- "./tests/vloghtb/common.sh")
- (("if ! which iverilog") "if ! true")
- (("iverilog ") (string-append iverilog " "))
- (("iverilog_bin=\".*\"") (string-append "iverilog_bin=\""
- iverilog "\"")))
- #t))))))
+ (lambda* (#:key inputs native-inputs #:allow-other-keys)
+ (let ((iverilog (search-input-file (or native-inputs inputs)
+ "/bin/iverilog")))
+ (substitute* '("./manual/CHAPTER_StateOfTheArt/synth.sh"
+ "./manual/CHAPTER_StateOfTheArt/validate_tb.sh"
+ "./techlibs/ice40/tests/test_bram.sh"
+ "./techlibs/ice40/tests/test_ffs.sh"
+ "./techlibs/xilinx/tests/bram1.sh"
+ "./techlibs/xilinx/tests/bram2.sh"
+ "./tests/bram/run-single.sh"
+ "./tests/realmath/run-test.sh"
+ "./tests/simple/run-test.sh"
+ "./tests/techmap/mem_simple_4x1_runtest.sh"
+ "./tests/tools/autotest.sh"
+ "./tests/vloghtb/common.sh")
+ (("if ! which iverilog") "if ! true")
+ (("iverilog ") (string-append iverilog " "))
+ (("iverilog_bin=\".*\"") (string-append "iverilog_bin=\""
+ iverilog "\"")))))))))
(native-inputs
- (list pkg-config
- python
- bison
+ (list bison
flex
gawk ; for the tests and "make" progress pretty-printing
- tcl ; tclsh for the tests
- iverilog)) ; for the tests
+ iverilog ; for the tests
+ pkg-config
+ python
+ tcl)) ; tclsh for the tests
(inputs
- (list tcl
- readline
- libffi
+ (list abc
graphviz
+ libffi
psmisc
- xdot
- abc))
+ readline
+ tcl
+ xdot))
(propagated-inputs
(list z3)) ; should be in path for yosys-smtbmc
(home-page "https://yosyshq.net/yosys/")
--
2.38.1
guix-patches@HIDDEN:bug#60429; Package guix-patches.
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From: Simon South <simon@HIDDEN>
To: 60429 <at> debbugs.gnu.org
Subject: [PATCH v2 4/5] gnu: yosys: Propagate external dependencies.
Date: Sun, 8 Jan 2023 13:31:30 -0500
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* gnu/packages/fpga.scm (yosys)[inputs]: Move graphviz, psmisc, xdot from
here...
[propagated-inputs]: ...to here, to ensure the availability at runtime of
executables invoked by yosys' "show" command.
[arguments]: Remove now-obsolete "fix-paths" phase.
---
gnu/packages/fpga.scm | 20 +++++---------------
1 file changed, 5 insertions(+), 15 deletions(-)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 8effebd921..785d385621 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -157,16 +157,6 @@ (define-public yosys
(string-append "PREFIX=" #$output))
#:phases
#~(modify-phases %standard-phases
- (add-before 'configure 'fix-paths
- (lambda* (#:key inputs #:allow-other-keys)
- (substitute* "./passes/cmds/show.cc"
- (("exec xdot")
- (string-append "exec " (search-input-file inputs
- "/bin/xdot")))
- (("dot -")
- (string-append (search-input-file inputs "/bin/dot") " -"))
- (("fuser")
- (search-input-file inputs "/bin/fuser")))))
(replace 'configure
(lambda* (#:key make-flags #:allow-other-keys)
(apply invoke "make" "config-gcc" make-flags)))
@@ -211,14 +201,14 @@ (define-public yosys
python
tcl)) ; tclsh for the tests
(inputs
- (list graphviz
- libffi
- psmisc
+ (list libffi
readline
- tcl
- xdot))
+ tcl))
(propagated-inputs
(list abc
+ graphviz ; for dot
+ psmisc ; for fuser
+ xdot
z3)) ; should be in path for yosys-smtbmc
(home-page "https://yosyshq.net/yosys/")
(synopsis "FPGA Verilog RTL synthesizer")
--
2.38.1
guix-patches@HIDDEN:bug#60429; Package guix-patches.
Full text available.
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From: Simon South <simon@HIDDEN>
To: 60429 <at> debbugs.gnu.org
Subject: [PATCH v2 1/5] gnu: yosys: Update source and home-page URLs.
Date: Sun, 8 Jan 2023 13:31:27 -0500
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* gnu/packages/fpga.scm (yosys)[source]: Update source-repository URL.
[home-page]: Update URL.
---
gnu/packages/fpga.scm | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index acce5f8f82..45aadf8ea4 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -141,7 +141,7 @@ (define-public yosys
(source (origin
(method git-fetch)
(uri (git-reference
- (url "https://github.com/cliffordwolf/yosys")
+ (url "https://github.com/YosysHQ/yosys")
(commit (string-append "yosys-" version))
(recursive? #t))) ; for the ‘iverilog’ submodule
(sha256
@@ -223,7 +223,7 @@ (define-public yosys
abc))
(propagated-inputs
(list z3)) ; should be in path for yosys-smtbmc
- (home-page "http://www.clifford.at/yosys/")
+ (home-page "https://yosyshq.net/yosys/")
(synopsis "FPGA Verilog RTL synthesizer")
(description "Yosys synthesizes Verilog-2005.")
(license license:isc)))
--
2.38.1
guix-patches@HIDDEN:bug#60429; Package guix-patches.
Full text available.
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From: Simon South <simon@HIDDEN>
To: 60429 <at> debbugs.gnu.org
Subject: [PATCH v2 3/5] gnu: yosys: Use external abc.
Date: Sun, 8 Jan 2023 13:31:29 -0500
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* gnu/packages/fpga.scm (yosys)[source]: Remove snippet and associated
"modules" field.
[arguments]: Replace "prepare-abc" phase with "use-external-abc", which
configures the package's build system to use the system's "abc" executable
instead of creating a duplicate; add "add-symbolic-link" phase to preserve
availability of "yosys-abc" command.
[inputs]: Move abc from here...
[propagated-inputs]: ...to here, to ensure its availability at runtime.
---
gnu/packages/fpga.scm | 35 +++++++++++++++++------------------
1 file changed, 17 insertions(+), 18 deletions(-)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 479ca3b061..8effebd921 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -147,12 +147,7 @@ (define-public yosys
(sha256
(base32
"0lb9r055h8y1vj2z8gm4ip0v06j5mk7f9zx9gi67kkqb7g4rhjli"))
- (file-name (git-file-name name version))
- (modules '((guix build utils)))
- (snippet
- #~(begin
- (substitute* "Makefile"
- (("ABCREV = .*") "ABCREV = default\n"))))))
+ (file-name (git-file-name name version))))
(build-system gnu-build-system)
(arguments
(list
@@ -175,14 +170,10 @@ (define-public yosys
(replace 'configure
(lambda* (#:key make-flags #:allow-other-keys)
(apply invoke "make" "config-gcc" make-flags)))
- (add-after 'configure 'prepare-abc
- (lambda* (#:key inputs #:allow-other-keys)
- (mkdir-p "abc")
- (call-with-output-file "abc/Makefile"
- (lambda (port)
- (format port ".PHONY: all\nall:\n\tcp -f abc abc-default\n")))
- (copy-file (search-input-file inputs "/bin/abc") "abc/abc")
- (invoke "chmod" "+w" "abc/abc")))
+ (add-after 'configure 'use-external-abc
+ (lambda _
+ (substitute* '("./Makefile")
+ (("ABCEXTERNAL \\?=") "ABCEXTERNAL = abc"))))
(add-before 'check 'fix-iverilog-references
(lambda* (#:key inputs native-inputs #:allow-other-keys)
(let ((iverilog (search-input-file (or native-inputs inputs)
@@ -202,7 +193,15 @@ (define-public yosys
(("if ! which iverilog") "if ! true")
(("iverilog ") (string-append iverilog " "))
(("iverilog_bin=\".*\"") (string-append "iverilog_bin=\""
- iverilog "\"")))))))))
+ iverilog "\""))))))
+ (add-after 'install 'add-symbolic-link
+ (lambda* (#:key inputs #:allow-other-keys)
+ ;; Previously this package provided a copy of the "abc"
+ ;; executable in its output, named "yosys-abc". Create a
+ ;; symbolic link so any external uses of that name continue to
+ ;; work.
+ (symlink (search-input-file inputs "/bin/abc")
+ (string-append #$output "/bin/yosys-abc")))))))
(native-inputs
(list bison
flex
@@ -212,15 +211,15 @@ (define-public yosys
python
tcl)) ; tclsh for the tests
(inputs
- (list abc
- graphviz
+ (list graphviz
libffi
psmisc
readline
tcl
xdot))
(propagated-inputs
- (list z3)) ; should be in path for yosys-smtbmc
+ (list abc
+ z3)) ; should be in path for yosys-smtbmc
(home-page "https://yosyshq.net/yosys/")
(synopsis "FPGA Verilog RTL synthesizer")
(description "Yosys synthesizes Verilog-2005.")
--
2.38.1
guix-patches@HIDDEN:bug#60429; Package guix-patches.
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From: Simon South <simon@HIDDEN>
To: 60429 <at> debbugs.gnu.org
Subject: [PATCH v2 0/5] gnu: yosys: Update to 0.24.
Date: Sun, 8 Jan 2023 13:31:26 -0500
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Here's a revised patchset with a modified final patch that updates yosys to
version 0.25, released in the past week, instead of 0.24. Everything else
remains unchanged.
I've re-tested this on x86-64 and AArch64 and everything appears fine.
Here's the original cover letter:
Here's a patch series that aims to improve the package for Yosys, a tool for
synthesizing Verilog RTL designs, by
- Updating the source-repository and home-page URLs to their current location;
- Updating the package definition to the modern style, using gexps and
search-input-file;
- Having Yosys use the "abc" executable from Guix's package rather than
creating and installing a duplicate copy;
- Explicitly propagating packages with executables Yosys invokes at runtime
rather than embedding store references in Yosys' code; and
- Updating Yosys to version 0.24.
I've tested building the package and its dependencies on x86-64 and AArch64
and everything seems okay[0]. Again, arachne-pnr fails to build in any case
and will need separate attention.
[0] Yosys' README.md file includes sample sessions useful for testing,
particularly whether external tools can be invoked via the "show" and
"abc" commands:
https://github.com/YosysHQ/yosys/blob/3ebc50d/README.md#getting-started
The files "fiedler-cooley.v" and "mycells.lib" are present in the source
tree.
--
Simon South
simon@HIDDEN
Simon South (5):
gnu: yosys: Update source and home-page URLs.
gnu: yosys: Use new package style.
gnu: yosys: Use external abc.
gnu: yosys: Propagate external dependencies.
gnu: yosys: Update to 0.25.
gnu/packages/fpga.scm | 120 ++++++++++++++++--------------------------
1 file changed, 45 insertions(+), 75 deletions(-)
base-commit: f5ea392b9cd3851ed7517876a8cd4beb13893c9c
--
2.38.1
guix-patches@HIDDEN:bug#60429; Package guix-patches.
Full text available.
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From: Simon South <simon@HIDDEN>
To: 60429 <at> debbugs.gnu.org
Subject: [PATCH 5/5] gnu: yosys: Update to 0.24.
Date: Fri, 30 Dec 2022 11:00:49 -0500
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* gnu/packages/fpga.scm (yosys): Update to 0.24.
[arguments]: Remove obsolete "fix-iverilog-references" phase.
[inputs]: Add zlib.
[propagated-inputs]: Add gtkwave, python, python-click.
---
gnu/packages/fpga.scm | 35 +++++++++--------------------------
1 file changed, 9 insertions(+), 26 deletions(-)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 785d385621..d3532069e8 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -137,16 +137,15 @@ (define-public iverilog
(define-public yosys
(package
(name "yosys")
- (version "0.9")
+ (version "0.24")
(source (origin
(method git-fetch)
(uri (git-reference
(url "https://github.com/YosysHQ/yosys")
- (commit (string-append "yosys-" version))
- (recursive? #t))) ; for the ‘iverilog’ submodule
+ (commit (string-append "yosys-" version))))
(sha256
- (base32
- "0lb9r055h8y1vj2z8gm4ip0v06j5mk7f9zx9gi67kkqb7g4rhjli"))
+ (base32
+ "1hrlqq9850j0160z9ibcia8fp0xxn0iakh0yb69kjzb6ffgjjn3d"))
(file-name (git-file-name name version))))
(build-system gnu-build-system)
(arguments
@@ -164,26 +163,6 @@ (define-public yosys
(lambda _
(substitute* '("./Makefile")
(("ABCEXTERNAL \\?=") "ABCEXTERNAL = abc"))))
- (add-before 'check 'fix-iverilog-references
- (lambda* (#:key inputs native-inputs #:allow-other-keys)
- (let ((iverilog (search-input-file (or native-inputs inputs)
- "/bin/iverilog")))
- (substitute* '("./manual/CHAPTER_StateOfTheArt/synth.sh"
- "./manual/CHAPTER_StateOfTheArt/validate_tb.sh"
- "./techlibs/ice40/tests/test_bram.sh"
- "./techlibs/ice40/tests/test_ffs.sh"
- "./techlibs/xilinx/tests/bram1.sh"
- "./techlibs/xilinx/tests/bram2.sh"
- "./tests/bram/run-single.sh"
- "./tests/realmath/run-test.sh"
- "./tests/simple/run-test.sh"
- "./tests/techmap/mem_simple_4x1_runtest.sh"
- "./tests/tools/autotest.sh"
- "./tests/vloghtb/common.sh")
- (("if ! which iverilog") "if ! true")
- (("iverilog ") (string-append iverilog " "))
- (("iverilog_bin=\".*\"") (string-append "iverilog_bin=\""
- iverilog "\""))))))
(add-after 'install 'add-symbolic-link
(lambda* (#:key inputs #:allow-other-keys)
;; Previously this package provided a copy of the "abc"
@@ -203,11 +182,15 @@ (define-public yosys
(inputs
(list libffi
readline
- tcl))
+ tcl
+ zlib))
(propagated-inputs
(list abc
graphviz ; for dot
+ gtkwave ; for vcd2fst
psmisc ; for fuser
+ python
+ python-click
xdot
z3)) ; should be in path for yosys-smtbmc
(home-page "https://yosyshq.net/yosys/")
--
2.38.1
guix-patches@HIDDEN:bug#60429; Package guix-patches.
Full text available.
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From: Simon South <simon@HIDDEN>
To: 60429 <at> debbugs.gnu.org
Subject: [PATCH 4/5] gnu: yosys: Propagate external dependencies.
Date: Fri, 30 Dec 2022 11:00:48 -0500
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* gnu/packages/fpga.scm (yosys)[inputs]: Move graphviz, psmisc, xdot from
here...
[propagated-inputs]: ...to here, to ensure the availability at runtime of
executables invoked by yosys' "show" command.
[arguments]: Remove now-obsolete "fix-paths" phase.
---
gnu/packages/fpga.scm | 20 +++++---------------
1 file changed, 5 insertions(+), 15 deletions(-)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 8effebd921..785d385621 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -157,16 +157,6 @@ (define-public yosys
(string-append "PREFIX=" #$output))
#:phases
#~(modify-phases %standard-phases
- (add-before 'configure 'fix-paths
- (lambda* (#:key inputs #:allow-other-keys)
- (substitute* "./passes/cmds/show.cc"
- (("exec xdot")
- (string-append "exec " (search-input-file inputs
- "/bin/xdot")))
- (("dot -")
- (string-append (search-input-file inputs "/bin/dot") " -"))
- (("fuser")
- (search-input-file inputs "/bin/fuser")))))
(replace 'configure
(lambda* (#:key make-flags #:allow-other-keys)
(apply invoke "make" "config-gcc" make-flags)))
@@ -211,14 +201,14 @@ (define-public yosys
python
tcl)) ; tclsh for the tests
(inputs
- (list graphviz
- libffi
- psmisc
+ (list libffi
readline
- tcl
- xdot))
+ tcl))
(propagated-inputs
(list abc
+ graphviz ; for dot
+ psmisc ; for fuser
+ xdot
z3)) ; should be in path for yosys-smtbmc
(home-page "https://yosyshq.net/yosys/")
(synopsis "FPGA Verilog RTL synthesizer")
--
2.38.1
guix-patches@HIDDEN:bug#60429; Package guix-patches.
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From: Simon South <simon@HIDDEN>
To: 60429 <at> debbugs.gnu.org
Subject: [PATCH 2/5] gnu: yosys: Use new package style.
Date: Fri, 30 Dec 2022 11:00:46 -0500
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* gnu/packages/fpga.scm (yosys)[source]: Use gexp in snippet and don't
explicitly return #t.
[arguments]: Use gexps; use search-input-file to locate executables; simplify
parameters to "configure" phase; don't explicitly return #t from phases.
[native-inputs]: Sort alphabetically.
[inputs]: Sort alphabetically.
---
gnu/packages/fpga.scm | 122 +++++++++++++++++++++---------------------
1 file changed, 60 insertions(+), 62 deletions(-)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 45aadf8ea4..479ca3b061 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -150,77 +150,75 @@ (define-public yosys
(file-name (git-file-name name version))
(modules '((guix build utils)))
(snippet
- '(begin
- (substitute* "Makefile"
- (("ABCREV = .*") "ABCREV = default\n"))
- #t))))
+ #~(begin
+ (substitute* "Makefile"
+ (("ABCREV = .*") "ABCREV = default\n"))))))
(build-system gnu-build-system)
(arguments
- `(#:test-target "test"
- #:make-flags (list "CC=gcc"
- "CXX=g++"
- (string-append "PREFIX=" %output))
- #:phases
- (modify-phases %standard-phases
- (add-before 'configure 'fix-paths
- (lambda _
- (substitute* "./passes/cmds/show.cc"
- (("exec xdot") (string-append "exec " (which "xdot")))
- (("dot -") (string-append (which "dot") " -"))
- (("fuser") (which "fuser")))
- #t))
- (replace 'configure
- (lambda* (#:key inputs (make-flags '()) #:allow-other-keys)
- (apply invoke "make" "config-gcc" make-flags)))
- (add-after 'configure 'prepare-abc
- (lambda* (#:key inputs #:allow-other-keys)
- (let* ((sourceabc (assoc-ref inputs "abc"))
- (sourcebin (string-append sourceabc "/bin"))
- (source (string-append sourcebin "/abc")))
- (mkdir-p "abc")
- (call-with-output-file "abc/Makefile"
- (lambda (port)
- (format port ".PHONY: all\nall:\n\tcp -f abc abc-default\n")))
- (copy-file source "abc/abc")
- (invoke "chmod" "+w" "abc/abc"))))
+ (list
+ #:test-target "test"
+ #:make-flags #~(list "CC=gcc"
+ "CXX=g++"
+ (string-append "PREFIX=" #$output))
+ #:phases
+ #~(modify-phases %standard-phases
+ (add-before 'configure 'fix-paths
+ (lambda* (#:key inputs #:allow-other-keys)
+ (substitute* "./passes/cmds/show.cc"
+ (("exec xdot")
+ (string-append "exec " (search-input-file inputs
+ "/bin/xdot")))
+ (("dot -")
+ (string-append (search-input-file inputs "/bin/dot") " -"))
+ (("fuser")
+ (search-input-file inputs "/bin/fuser")))))
+ (replace 'configure
+ (lambda* (#:key make-flags #:allow-other-keys)
+ (apply invoke "make" "config-gcc" make-flags)))
+ (add-after 'configure 'prepare-abc
+ (lambda* (#:key inputs #:allow-other-keys)
+ (mkdir-p "abc")
+ (call-with-output-file "abc/Makefile"
+ (lambda (port)
+ (format port ".PHONY: all\nall:\n\tcp -f abc abc-default\n")))
+ (copy-file (search-input-file inputs "/bin/abc") "abc/abc")
+ (invoke "chmod" "+w" "abc/abc")))
(add-before 'check 'fix-iverilog-references
- (lambda* (#:key inputs native-inputs #:allow-other-keys)
- (let* ((xinputs (or native-inputs inputs))
- (xdirname (assoc-ref xinputs "iverilog"))
- (iverilog (string-append xdirname "/bin/iverilog")))
- (substitute* '("./manual/CHAPTER_StateOfTheArt/synth.sh"
- "./manual/CHAPTER_StateOfTheArt/validate_tb.sh"
- "./techlibs/ice40/tests/test_bram.sh"
- "./techlibs/ice40/tests/test_ffs.sh"
- "./techlibs/xilinx/tests/bram1.sh"
- "./techlibs/xilinx/tests/bram2.sh"
- "./tests/bram/run-single.sh"
- "./tests/realmath/run-test.sh"
- "./tests/simple/run-test.sh"
- "./tests/techmap/mem_simple_4x1_runtest.sh"
- "./tests/tools/autotest.sh"
- "./tests/vloghtb/common.sh")
- (("if ! which iverilog") "if ! true")
- (("iverilog ") (string-append iverilog " "))
- (("iverilog_bin=\".*\"") (string-append "iverilog_bin=\""
- iverilog "\"")))
- #t))))))
+ (lambda* (#:key inputs native-inputs #:allow-other-keys)
+ (let ((iverilog (search-input-file (or native-inputs inputs)
+ "/bin/iverilog")))
+ (substitute* '("./manual/CHAPTER_StateOfTheArt/synth.sh"
+ "./manual/CHAPTER_StateOfTheArt/validate_tb.sh"
+ "./techlibs/ice40/tests/test_bram.sh"
+ "./techlibs/ice40/tests/test_ffs.sh"
+ "./techlibs/xilinx/tests/bram1.sh"
+ "./techlibs/xilinx/tests/bram2.sh"
+ "./tests/bram/run-single.sh"
+ "./tests/realmath/run-test.sh"
+ "./tests/simple/run-test.sh"
+ "./tests/techmap/mem_simple_4x1_runtest.sh"
+ "./tests/tools/autotest.sh"
+ "./tests/vloghtb/common.sh")
+ (("if ! which iverilog") "if ! true")
+ (("iverilog ") (string-append iverilog " "))
+ (("iverilog_bin=\".*\"") (string-append "iverilog_bin=\""
+ iverilog "\"")))))))))
(native-inputs
- (list pkg-config
- python
- bison
+ (list bison
flex
gawk ; for the tests and "make" progress pretty-printing
- tcl ; tclsh for the tests
- iverilog)) ; for the tests
+ iverilog ; for the tests
+ pkg-config
+ python
+ tcl)) ; tclsh for the tests
(inputs
- (list tcl
- readline
- libffi
+ (list abc
graphviz
+ libffi
psmisc
- xdot
- abc))
+ readline
+ tcl
+ xdot))
(propagated-inputs
(list z3)) ; should be in path for yosys-smtbmc
(home-page "https://yosyshq.net/yosys/")
--
2.38.1
guix-patches@HIDDEN:bug#60429; Package guix-patches.
Full text available.
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From: Simon South <simon@HIDDEN>
To: 60429 <at> debbugs.gnu.org
Subject: [PATCH 3/5] gnu: yosys: Use external abc.
Date: Fri, 30 Dec 2022 11:00:47 -0500
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* gnu/packages/fpga.scm (yosys)[source]: Remove snippet and associated
"modules" field.
[arguments]: Replace "prepare-abc" phase with "use-external-abc", which
configures the package's build system to use the system's "abc" executable
instead of creating a duplicate; add "add-symbolic-link" phase to preserve
availability of "yosys-abc" command.
[inputs]: Move abc from here...
[propagated-inputs]: ...to here, to ensure its availability at runtime.
---
gnu/packages/fpga.scm | 35 +++++++++++++++++------------------
1 file changed, 17 insertions(+), 18 deletions(-)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 479ca3b061..8effebd921 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -147,12 +147,7 @@ (define-public yosys
(sha256
(base32
"0lb9r055h8y1vj2z8gm4ip0v06j5mk7f9zx9gi67kkqb7g4rhjli"))
- (file-name (git-file-name name version))
- (modules '((guix build utils)))
- (snippet
- #~(begin
- (substitute* "Makefile"
- (("ABCREV = .*") "ABCREV = default\n"))))))
+ (file-name (git-file-name name version))))
(build-system gnu-build-system)
(arguments
(list
@@ -175,14 +170,10 @@ (define-public yosys
(replace 'configure
(lambda* (#:key make-flags #:allow-other-keys)
(apply invoke "make" "config-gcc" make-flags)))
- (add-after 'configure 'prepare-abc
- (lambda* (#:key inputs #:allow-other-keys)
- (mkdir-p "abc")
- (call-with-output-file "abc/Makefile"
- (lambda (port)
- (format port ".PHONY: all\nall:\n\tcp -f abc abc-default\n")))
- (copy-file (search-input-file inputs "/bin/abc") "abc/abc")
- (invoke "chmod" "+w" "abc/abc")))
+ (add-after 'configure 'use-external-abc
+ (lambda _
+ (substitute* '("./Makefile")
+ (("ABCEXTERNAL \\?=") "ABCEXTERNAL = abc"))))
(add-before 'check 'fix-iverilog-references
(lambda* (#:key inputs native-inputs #:allow-other-keys)
(let ((iverilog (search-input-file (or native-inputs inputs)
@@ -202,7 +193,15 @@ (define-public yosys
(("if ! which iverilog") "if ! true")
(("iverilog ") (string-append iverilog " "))
(("iverilog_bin=\".*\"") (string-append "iverilog_bin=\""
- iverilog "\"")))))))))
+ iverilog "\""))))))
+ (add-after 'install 'add-symbolic-link
+ (lambda* (#:key inputs #:allow-other-keys)
+ ;; Previously this package provided a copy of the "abc"
+ ;; executable in its output, named "yosys-abc". Create a
+ ;; symbolic link so any external uses of that name continue to
+ ;; work.
+ (symlink (search-input-file inputs "/bin/abc")
+ (string-append #$output "/bin/yosys-abc")))))))
(native-inputs
(list bison
flex
@@ -212,15 +211,15 @@ (define-public yosys
python
tcl)) ; tclsh for the tests
(inputs
- (list abc
- graphviz
+ (list graphviz
libffi
psmisc
readline
tcl
xdot))
(propagated-inputs
- (list z3)) ; should be in path for yosys-smtbmc
+ (list abc
+ z3)) ; should be in path for yosys-smtbmc
(home-page "https://yosyshq.net/yosys/")
(synopsis "FPGA Verilog RTL synthesizer")
(description "Yosys synthesizes Verilog-2005.")
--
2.38.1
guix-patches@HIDDEN:bug#60429; Package guix-patches.
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From: Simon South <simon@HIDDEN>
To: 60429 <at> debbugs.gnu.org
Subject: [PATCH 1/5] gnu: yosys: Update source and home-page URLs.
Date: Fri, 30 Dec 2022 11:00:45 -0500
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* gnu/packages/fpga.scm (yosys)[source]: Update source-repository URL.
[home-page]: Update URL.
---
gnu/packages/fpga.scm | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index acce5f8f82..45aadf8ea4 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -141,7 +141,7 @@ (define-public yosys
(source (origin
(method git-fetch)
(uri (git-reference
- (url "https://github.com/cliffordwolf/yosys")
+ (url "https://github.com/YosysHQ/yosys")
(commit (string-append "yosys-" version))
(recursive? #t))) ; for the ‘iverilog’ submodule
(sha256
@@ -223,7 +223,7 @@ (define-public yosys
abc))
(propagated-inputs
(list z3)) ; should be in path for yosys-smtbmc
- (home-page "http://www.clifford.at/yosys/")
+ (home-page "https://yosyshq.net/yosys/")
(synopsis "FPGA Verilog RTL synthesizer")
(description "Yosys synthesizes Verilog-2005.")
(license license:isc)))
--
2.38.1
guix-patches@HIDDEN:bug#60429; Package guix-patches.
Full text available.
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From: Simon South <simon@HIDDEN>
To: guix-patches@HIDDEN
Subject: [PATCH 0/5] gnu: yosys: Update to 0.24.
Date: Fri, 30 Dec 2022 10:58:32 -0500
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Here's a patch series that aims to improve the package for Yosys, a tool for
synthesizing Verilog RTL designs, by
- Updating the source-repository and home-page URLs to their current location;
- Updating the package definition to the modern style, using gexps and
search-input-file;
- Having Yosys use the "abc" executable from Guix's package rather than
creating and installing a duplicate copy;
- Explicitly propagating packages with executables Yosys invokes at runtime
rather than embedding store references in Yosys' code; and
- Updating Yosys to version 0.24.
I've tested building the package and its dependencies on x86-64 and AArch64
and everything seems okay[0]. Again, arachne-pnr fails to build in any case
and will need separate attention.
[0] Yosys' README.md file includes sample sessions useful for testing,
particularly whether external tools can be invoked via the "show" and
"abc" commands:
https://github.com/YosysHQ/yosys/blob/3ebc50d/README.md#getting-started
The files "fiedler-cooley.v" and "mycells.lib" are present in the source
tree.
--
Simon South
simon@HIDDEN
Simon South (5):
gnu: yosys: Update source and home-page URLs.
gnu: yosys: Use new package style.
gnu: yosys: Use external abc.
gnu: yosys: Propagate external dependencies.
gnu: yosys: Update to 0.24.
gnu/packages/fpga.scm | 120 ++++++++++++++++--------------------------
1 file changed, 45 insertions(+), 75 deletions(-)
base-commit: 01762b7171f9afaf7ffa364f7926461bdebc903f
--
2.38.1
Simon South <simon@HIDDEN>:guix-patches@HIDDEN.
Full text available.guix-patches@HIDDEN:bug#60429; Package guix-patches.
Full text available.
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